1. Field of the Invention
The present invention relates to semiconductor chips for a so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded in a double-stacked relation, chip-on-chip semiconductor devices, and chip-on-chip mounting methods.
2. Description of Related Art
For size reduction and higher integration of semiconductor devices, a proposal has been made to shift the design concept from a conventional two-dimensional structure to a three-dimensional structure.
However, production of semiconductor devices of three-dimensional structure through a continuous process often encounters difficulties such as a lower yield.
The inventors of the present invention have been conducting studies on practical applications of a semiconductor device of so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded to one another in a face-to-face double-stacked relation.
Where semiconductor chips are bonded to each other in a stacked relation, for example, where a relatively small secondary chip is laid on the front face of a relatively large primary chip, the secondary chip can easily be positioned in alignment with the primary chip with the front face thereof upward and with the back face thereof opposed to the front face of the primary chip.
However, if an attempt is made to stack the primary chip and the secondary chip in a face-to-face relation, there is a difficulty in aligning these semiconductor chips with each other. This is because the orientation of a semiconductor chip, the arrangement of electrodes on the front face of the semiconductor chip and the like cannot be checked from the back side thereof.
Particularly, the electrodes are not always arranged in a predetermined positional relationship with the profile of the semiconductor chip, but the positional relationship between the electrode arrangement and the profile varies depending on dicing conditions under which a semiconductor wafer is diced into semiconductor chips. Therefore, it is difficult to align or position the semiconductor chips with respect to each other by viewing either of the semiconductor chips from the back side thereof.
Even if the primary and secondary chips have substantially the same size, the alignment of the semiconductor chips for bonding thereof is difficult.